The present invention relates to a thin-film electroluminescent device for providing an improved optical display and more particularly to an improved active matrix thin film electroluminescent device (AMEL) for use as an optical display.
In general, AMEL displays are constructed of a thin-film laminar stack comprising a set of transparent front electrodes carrying an illumination signal, which are typically indium tin oxide deposited on a transparent substrate (glass). A transparent electroluminescent phosphor layer is sandwiched between front and rear dielectric layers, all of which is deposited behind the front electrodes. Pixel electrodes are deposited on the rear dielectric layer, typically consisting of a pad of metal or poly-silicon, positioned at each location a pixel is desired within the phosphor layer. An insulator made of any suitable material, such as SiO.sub.2 or glass, is deposited on the pixel electrodes and exposed rear dielectric layer. The insulator layer is preferably constructed with holes in the insulator layer commonly referred to as VIA for each pixel electrode, to permit the connection of the pixel electrodes to a circuit layer which is deposited on the insulator layer. The circuit layer permits the individual addressing of each pixel electrode. As such, an individual pixel within the electroluminescent layer may be selectively illuminated by the circuit layer permitting a sufficient electrical field to be created between the front electrodes and the respective pixel electrode.
Referring to FIG. 1, an electrical schematic of an AMEL device is shown. A circuit layer 10 for selectively illuminating a respective pixel, is constructed with a low voltage transistor 12, that is designed to handle signals up to the range of about 20 volts, to gate a data signal (voltage signal) from a data line 14 connected to the low voltage transistor's source 16 to the low voltage transistor's drain 18. The drain 18 is connected to a hold capacitor 20 which in turn is connected to a ground line 26. In an actual fabricated AMEL device, the capacitor 20 is not generally fabricated as a discrete element, but is the capacitance of the line 40 between the low voltage transistor's drain 18 and the high voltage transistor's gate 30, coupled to the ground line 26. The gate 22 of the low voltage transistor 12 is connected to a select line 24 for activating the low voltage transistor 12 to permit selective gating of the data signal to the hold capacitor 20 for temporary storage. After gating the data signal to the hold capacitor 20, the select line 24 is typically then deselected, thereby, isolating the hold capacitor 20 from the data line 14. The capacitor 20 maintains the applied voltage for a period of time sufficient for the illumination of a pixel. The capacitor 20 is also connected to the gate 30 of a high voltage transistor 28, which is designed to withstand voltages in the range of about 200 volts (which typically is the maximum voltage applied to a display). Fabricating a high voltage transistor to maintain about 200 volts between its terminals is difficult and expensive. Such high voltage transistors also require a significant amount of area that may not be available when high resolution displays are constructed. Further, the high voltage transistors may not be as reliable as needed for cost effective manufacturing.
The high voltage transistor's source 29 and drain 31 are respectively connected between the ground line 26 and a pixel electrode 32. The front electrodes 34 carry a high AC voltage illumination signal powered by a signal driver 36. By activating the gate 30 of the high voltage transistor 28 with the electrical charge stored in the capacitor 20, after the low voltage transistor 22 has been deactivated, or by the data signal directly when the low voltage transistor 12 is activated, the pixel electrode 32 is electrically connected to the ground line 26 through transistor 28. By connecting the pixel electrode 32 to the ground line 26 a sufficient electric field is created between the respective portion of the front electrodes 34 and the pixel electrode 32, causing light to be emitted from the interposed electroluminescent layer 38.
A disadvantage of using this particular circuit design, in addition to the problems associated with the high voltage transistor 30, is that each line, namely the ground line 26, data line 14, select line 24, and front electrodes 34 (illumination line), each requires a level of metalization during the fabrication of the display, and with it the associated cost and process complexity to implement each level of metalization. If one or more lines could be eliminated, then a decrease in the manufacturing cost and process complexity might be realized.
Referring to FIG. 2, a modified design of the circuit layer 10 is shown that does eliminate a metalized line. The modified design involves connecting the source 57 of the high voltage transistor 54 to the data line 55 and the capacitor 56 to ground. This circuit layer 50 reduces the required number of lines from four to three by elimination of the ground line 26. This design works adequately at low refresh rates. However, this design seriously limits maximum refresh rate achievable because the data signal cannot be stored in the capacitor 56 simultaneously with the illumination of the pixel due to the connection of the high voltage transistor 54 with the data line 55. As an illustration of the problem, if a high data bit is written to the data line 55, the low voltage transistor 58 will apply a charge to the capacitor 56 if the select line 61 activates the gate 59 of the low voltage transistor 58. This in turn imposes a high voltage at the gate 66 of the high voltage transistor 54. The high voltage transistor 54 will not be activated because the high data bit data signal is also simultaneously imposed on the drain 57 of the high voltage transistor 54. This causes the respective pixel in the phosphor layer, to be turned off if it was previously on, or, if it was previously off to delay illuminating (turned on) because a sufficient electric field will not be created between the front electrodes 65 and the respective pixel electrode 64 until the high voltage transistor 54 is activated. However, the high voltage transistor 54 will not be activated until a high voltage is at the high voltage transistor's gate 66 and the data line 55 is grounded.
The limitation of not having the capability of simultaneously writing data and illuminating the respective pixel reduces the illumination time of the pixel by the period of time required to write the data. This limitation is minor when low refresh rates are used, but becomes pronounced when employing high refresh rates, such as when a temporal gray scale approach is used, because the whole display needs to be updated by the number of gray scales desired during each screen refresh. In other words, when using a gray scale display, the pixels need to be turned on and off at a much higher rate than would normally be the case, and the time period necessary to write the data becomes more significant with respect to the illumination time.
Additionally, the reduction in the illumination time proportionately decreases the maximum possible brightness of the display and also requires faster data update rates due to the shorter time allowed. Furthermore, since the data line 55 is used to both write the data and sink large electroluminescent currents when the high voltage transistor 54 is activated, the data line 55 will need to be a low resistance line to be able to accommodate the increased current levels. However, such low resistance data lines 55 are difficult to fabricate. Furthermore, a higher sinking capability is required for a driver 60 controlling the data line 55.
Vanfleteren, et al., Evaluation Of A 64.times.64 CdSe TFT Addressed ACTFEL Display Demonstrator, discloses in FIG. 1 a two transistor-two capacitor circuit for driving an AMEL electroluminescent device. In this circuit design, C.sub.v is provided between the high voltage transistor and the electroluminescent stack to reduce the voltage on the high voltage transistor when it is off. A voltage divider is formed with C.sub.El and C.sub.v in a manner so that the high voltage transistor does not operate in the breakdown region because traditional wisdom is that the high voltage transistor will self-destruct if required to do so. With large pixels, such as those in the Vanfleteren disclosure, there is a high capacitance value which causes peak currents that may be too large for the high voltage transistors to handle. Additionally, using large pixels increases the chances of microscopic shorts that can result in a direct current destroying the high voltage transistor. The fabrication of C.sub.v also takes a significant amount of area, additional processing, and is a high voltage capacitor that could fail reducing the yield of manufacturing.
Referring to FIG. 2 of Vanfleteren, et al., the structure of the AMEL device is constructed by starting with a glass layer and then proceeding to deposit an ITO, dielectric, phosphor, and dielectric layer. Then, the pixel electrodes are deposited on the last dielectric layer followed by a sandwiched layer structure of a first Al.sub.2 O.sub.3 layer, a second Al.sub.2 O.sub.3 layer and a grounded electrode layer between the first and second Al.sub.2 O.sub.3 layers. Deposited on the second Al.sub.2 O.sub.3 layer are the individual circuit elements forming a circuit layer. Large voltages are present during the operation of the display between the ITO and the pixel electrodes that produce stray voltages that could easily interfere with the transistors, particularly the low voltage transistor in the circuit layer. The interposed grounded electrode layer between the Al.sub.2 O.sub.3 layers acts to shield the circuit layer from the stray voltages, thus reducing the likelihood of interference with the operation of the circuit layer. The second Al.sub.2 O.sub.3 layer will inherently have a significant number of microscopic defects due to depositing it on the grounded electrode layer which limits how small the individual circuit elements may be and still function. As described in Vanfleteren, the low power memory TFT has channel dimensions of W.times.L=25 .mu.m.times.125 .mu.m which is totally unacceptable when constructing a high resolution display. Such channel dimensions and the circuit used in Vanfleteren will probably only give a maximum resolution of around 100 pixels per inch.
What is desirable is a display structure that minimizes the number of lines required in an AMEL circuit layer and permits the use of significantly smaller transistors and other circuit elements, so that high resolution displays up to the range of 2,000 pixels per inch can be manufactured. Further, the design should provide for high maximum refresh rates to accommodate a high gray scale.